PET System Synchronization and Timing Resolution Using High-Speed Data Links

Research areas:
Authors:
Aliaga, R. J.; Monzo, J. M.; Spaggiari, M.; Ferrando, N.; Gadea, R.; Colom, R. J.
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2011
Article
IEEE Transactions on Nuclear Science
58
4
1596-1605
August
018--9499
Keywords:
Data acquisition, positron emission tomography , serial links , synchronization , timing resolution

 

Abstract:
Current PET systems with fully digital trigger rely on early digitization of detector signals and the use of digital processors, usually FPGAs, for recognition of valid gamma events on single detectors. Timestamps are assigned and later used for coincidence analysis. In order to maintain a decent timing resolution for events detected on different acquisition boards, it is necessary that local timestamps on different FPGAs be synchronized. Sub-nanosecond accuracy is mandatory if we want this effect to be negligible on overall timing resolution. This is usually achieved by connecting all boards to a common backplane with a precise clock delivery network; however, this approach forces a rigid structure on the whole PET system and may pose scalability problems. As an alternative, we propose a backplane-less PET system architecture in which DAQ boards are connected by single full-duplex high-speed data links. Data encoding with embedded clock is used to correct frequency differences between local oscillators. Timestamp synchronization between FPGAs with clock period resolution is maintained by means of data transfers in a way similar to the IEEE 1588 standard. Finer resolution is achieved by reflection of received clocks and phase difference measurement on the transmitter. It is crucial that data transceivers have very low latency uncertainty in order to achieve the desired timestamp accuracy; we discuss the availability of off-the-shelf hardware for these implementations.

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Digital Signal Processing Techniques to Improve Time Resolution in Positron Emission Tomography

Research areas:
Authors:
Monzo, J.; Esteve, R.; Lerche, C.; Ferrando, N.; Toledo, J.; Aliaga, R.; Herrero, V.; Mora, F.
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2011
Article
IEEE Transactions on Nuclear Science
58
4
1613-
1620
August
0018-
9499
Keywords:
Constant fraction discriminator , digital signal processing , field-programmable gate array, FPGA, positron emission tomography, time resolution , timing algorithms

Abstract:
Coincidence time resolution is one of the most important issues in PET detectors. Improving this resolution is required to increase the noise equivalent count rate (NECR) that reduces the noise in the reconstructed images. The aim of this work is to evaluate the behavior and time resolution of different proposed time pick-off algorithms in order to select the best configuration for our PET system. The experimental setup used for this research is composed by two monolithic LSO crystals+PSPMT detectors and an FPGA based PET data acquisition system (DAQ). The acquired signals are sampled using a 12-bit 70 MHz analog to digital converter (ADC) per channel. The setup has no centralized electronics for trigger and event time extraction. Consequently, events for each detector head are processed independently and all the signals are acquired in the same way. Time resolution in this kind of systems can be improved by means of digital processing techniques and using different shapings for the last dynode signals. Four digital algorithms extracting time information from the acquired pulses have been evaluated: (1) Amplitude bipolar digital constant fraction discriminator (BCFD), (2) charge BCFD, (3) interpolated amplitude BCFD and (4) interpolated charge BCFD. Two different architectures for the interpolation algorithm have been used (one-sample and two-sample interpolation), which allow us to work with two different FPGA internal sampling frequencies: 140 MHz and 210 MHz. The results show the importance of selecting the right algorithm and parameters. Time coincidence resolution in our hardware system can be improved by up to 6.9 ns FWHM depending on the chosen digital algorithm programmed on the FPGA. The measurements with our setup reveal that charge based algorithms are less sensitive to signal noise and generate better results than amplitude algorithms. The best configuration achieves a FWHM resolution close to 1.8 ns.

Online version

The front-end concentrator card for the RD51 scalable readout system

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Authors:
Toledo, J.; Muller, H.; Esteve, R.; Monzó, J. M.; Tarazona, A.; Martoiu, S.
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2011
Article
Journal of Instrumentation
6
November
Keywords:
Data acquisition concepts, Electronic detector readout concepts, Data acquisition circuits

 

Abstract:
Conventional readout systems exist in many variants since the usual approach is to build readout electronics for one given type of detector. The Scalable Readout System (SRS) developed within the RD51 collaboration relaxes this situation considerably by providing a choice of frontends which are connected over a customizable interface to a common SRS DAQ architecture. This allows sharing development and production costs among a large base of users as well as support from a wide base of developers. The Front-end Concentrator card (FEC), a RD51 common project between CERN and the NEXT Collaboration, is a reconfigurable interface between the SRS online system and a wide range of frontends. This is accomplished by using application-specific adapter cards between the FEC and the frontends. The ensemble (FEC and adapter card are edge mounted) forms a 6U × 220 mm Eurocard combo that fits on a 19'' subchassis. Adapter cards exist already for the first applications and more are in development.

Online version

Readout electronics for the SiPM tracking plane in the NEXT-1 prototype

Research areas:
Authors:
Herrero, V.; Toledo, J.; Català, J. M.; Esteve, R.; Gil, A.; Lorca, D.; Monzó, J. M.; Sanchis, F.; Verdugo, A.
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Type of Publication:
Journal:
 
2011
Article
Nucl. Instrum. Meth. Phys. Res. A
 
Keywords:
Neutrinoless double beta decay, Xenon gas TPC, SiPM readout, Front-end electronics, Gated integrator

 

Abstract:
NEXT is a new experiment to search for neutrinoless double beta decay using a 100 kg radio-pure high-pressure gaseous xenon TPC with electroluminescence readout. A large-scale prototype with a SiPM tracking plane has been built. The primary electron paths can be reconstructed from time-resolved measurements of the light that arrives to the SiPM plane. Our approach is to measure how many photons have reached each SiPM sensor each microsecond with a gated integrator. We have designed and tested a 16-channel front-end board that includes the analog paths and a digital section. Each analog path consists of three different stages: a transimpedance amplifier, a gated integrator and an offset and gain control stage. Measurements show good linearity and the ability to detect single photoelectrons.

Online version

AMIC: An expandable integrated analog front-end for light distribution moment analysis

Research areas:
Authors:
Spaggiari, M.; Herrero, V.; Lerche, C. W.; Aliaga, R.; Monzó, J. M.; Gadea, R.
Year:
Type of Publication:
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Volume:
2011
Article
JINST
6
Keywords:
Analogue electronic circuits, Gamma camera, SPECT, PET PET-CT, coronary CT angiography, Front-end electronics for detector readout

 

Abstract:
In this article we introduce AMIC (Analog Moments Integrated Circuit), a novel analog Application Specific Integrated Circuit (ASIC) front-end for Positron Emission Tomography (PET) applications. Its working principle is based on mathematical analysis of light distribution through moments calculation. Each moment provides useful information about light distribution, such as energy, position, depth of interaction, skewness (deformation due to border effect) etc. A current buffer delivers a copy of each input current to several processing blocks. The current preamplifier is designed in order to achieve unconditional stability under high input capacitance, thus allowing the use of both Photo-Multiplier Tubes (PMT) and Silicon Photo-Multipliers (SiPM). Each processing block implements an analog current filtering by multiplying each input current by a programmable 8-bit coefficient. The latter is implemented through a high linear MOS current divider ladder, whose high sensitivity to variations in output voltages requires the integration of an extremely stable fully differential current collector. Output currents are then summed and sent to the output stage, that provides both a buffered output current and a linear rail-to-rail voltage for further digitalization. Since computation is purely additive, the 64 input channels of AMIC do not represent a limitation in the number of the detector’s outputs. Current outputs of various AMIC structures can be combined as inputs of a final AMIC, thus providing a fully expandable structure. In this version of AMIC, 8 programmable blocks for moments calculation are integrated, as well as an I2C interface in order to program every coefficient. Extracted layout simulation results demonstrate that the information provided by moment calculation in AMIC helps to improve tridimensional positioning of the detected event. A two-detector test-bench is now being used for AMIC prototype characterization and preliminary results are presented.

Online version